/*
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* Distributed under the Boost Software License, Version 1.0.
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* (See accompanying file LICENSE_1_0.txt or copy at
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* http://www.boost.org/LICENSE_1_0.txt)
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*
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* Copyright (c) 2009 Helge Bahmann
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* Copyright (c) 2013 Tim Blechmann
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* Copyright (c) 2014 Andrey Semashev
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*/
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/*!
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* \file atomic/detail/core_arch_ops_gcc_alpha.hpp
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*
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* This header contains implementation of the \c core_arch_operations template.
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*/
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#ifndef BOOST_ATOMIC_DETAIL_CORE_ARCH_OPS_GCC_ALPHA_HPP_INCLUDED_
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#define BOOST_ATOMIC_DETAIL_CORE_ARCH_OPS_GCC_ALPHA_HPP_INCLUDED_
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#include <cstddef>
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#include <boost/memory_order.hpp>
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#include <boost/atomic/detail/config.hpp>
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#include <boost/atomic/detail/storage_traits.hpp>
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#include <boost/atomic/detail/core_arch_operations_fwd.hpp>
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#include <boost/atomic/detail/header.hpp>
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#ifdef BOOST_HAS_PRAGMA_ONCE
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#pragma once
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#endif
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namespace boost {
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namespace atomics {
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namespace detail {
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/*
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Refer to http://h71000.www7.hp.com/doc/82final/5601/5601pro_004.html
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(HP OpenVMS systems documentation) and the Alpha Architecture Reference Manual.
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*/
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/*
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NB: The most natural thing would be to write the increment/decrement
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operators along the following lines:
|
|
__asm__ __volatile__
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(
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"1: ldl_l %0,%1 \n"
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"addl %0,1,%0 \n"
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"stl_c %0,%1 \n"
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"beq %0,1b\n"
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: "=&b" (tmp)
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: "m" (value)
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: "cc"
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);
|
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However according to the comments on the HP website and matching
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comments in the Linux kernel sources this defies branch prediction,
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as the cpu assumes that backward branches are always taken; so
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instead copy the trick from the Linux kernel, introduce a forward
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branch and back again.
|
|
I have, however, had a hard time measuring the difference between
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the two versions in microbenchmarks -- I am leaving it in nevertheless
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as it apparently does not hurt either.
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*/
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struct core_arch_operations_gcc_alpha_base
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{
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static BOOST_CONSTEXPR_OR_CONST bool full_cas_based = false;
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static BOOST_CONSTEXPR_OR_CONST bool is_always_lock_free = true;
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static BOOST_FORCEINLINE void fence_before(memory_order order) BOOST_NOEXCEPT
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{
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if ((static_cast< unsigned int >(order) & static_cast< unsigned int >(memory_order_release)) != 0u)
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__asm__ __volatile__ ("mb" ::: "memory");
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}
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static BOOST_FORCEINLINE void fence_after(memory_order order) BOOST_NOEXCEPT
|
{
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if ((static_cast< unsigned int >(order) & (static_cast< unsigned int >(memory_order_consume) | static_cast< unsigned int >(memory_order_acquire))) != 0u)
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__asm__ __volatile__ ("mb" ::: "memory");
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}
|
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static BOOST_FORCEINLINE void fence_after_store(memory_order order) BOOST_NOEXCEPT
|
{
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if (order == memory_order_seq_cst)
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__asm__ __volatile__ ("mb" ::: "memory");
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}
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};
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|
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template< bool Signed, bool Interprocess >
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struct core_arch_operations< 4u, Signed, Interprocess > :
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public core_arch_operations_gcc_alpha_base
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{
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typedef typename storage_traits< 4u >::type storage_type;
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static BOOST_CONSTEXPR_OR_CONST std::size_t storage_size = 4u;
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static BOOST_CONSTEXPR_OR_CONST std::size_t storage_alignment = 4u;
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static BOOST_CONSTEXPR_OR_CONST bool is_signed = Signed;
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static BOOST_CONSTEXPR_OR_CONST bool is_interprocess = Interprocess;
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static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
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{
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fence_before(order);
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storage = v;
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fence_after_store(order);
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}
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static BOOST_FORCEINLINE storage_type load(storage_type const volatile& storage, memory_order order) BOOST_NOEXCEPT
|
{
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storage_type v = storage;
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fence_after(order);
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return v;
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}
|
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static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
|
{
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storage_type original, tmp;
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fence_before(order);
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__asm__ __volatile__
|
(
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"1:\n\t"
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"mov %3, %1\n\t"
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"ldl_l %0, %2\n\t"
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"stl_c %1, %2\n\t"
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"beq %1, 2f\n\t"
|
|
".subsection 2\n\t"
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"2: br 1b\n\t"
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".previous\n\t"
|
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: "=&r" (original), // %0
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"=&r" (tmp) // %1
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: "m" (storage), // %2
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"r" (v) // %3
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: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
|
);
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fence_after(order);
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return original;
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}
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static BOOST_FORCEINLINE bool compare_exchange_weak(
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storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
|
{
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fence_before(success_order);
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int success;
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storage_type current;
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__asm__ __volatile__
|
(
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"1:\n\t"
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"ldl_l %2, %4\n\t" // current = *(&storage)
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"cmpeq %2, %0, %3\n\t" // success = current == expected
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"mov %2, %0\n\t" // expected = current
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"beq %3, 2f\n\t" // if (success == 0) goto end
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"stl_c %1, %4\n\t" // storage = desired; desired = store succeeded
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"mov %1, %3\n\t" // success = desired
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"2:\n\t"
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: "+r" (expected), // %0
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"+r" (desired), // %1
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"=&r" (current), // %2
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"=&r" (success) // %3
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: "m" (storage) // %4
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: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
|
);
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if (success)
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fence_after(success_order);
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else
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fence_after(failure_order);
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return !!success;
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}
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static BOOST_FORCEINLINE bool compare_exchange_strong(
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storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
|
{
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int success;
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storage_type current, tmp;
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fence_before(success_order);
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__asm__ __volatile__
|
(
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"1:\n\t"
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"mov %5, %1\n\t" // tmp = desired
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"ldl_l %2, %4\n\t" // current = *(&storage)
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"cmpeq %2, %0, %3\n\t" // success = current == expected
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"mov %2, %0\n\t" // expected = current
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"beq %3, 2f\n\t" // if (success == 0) goto end
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"stl_c %1, %4\n\t" // storage = tmp; tmp = store succeeded
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"beq %1, 3f\n\t" // if (tmp == 0) goto retry
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"mov %1, %3\n\t" // success = tmp
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"2:\n\t"
|
|
".subsection 2\n\t"
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"3: br 1b\n\t"
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".previous\n\t"
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: "+r" (expected), // %0
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"=&r" (tmp), // %1
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"=&r" (current), // %2
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"=&r" (success) // %3
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: "m" (storage), // %4
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"r" (desired) // %5
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: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
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);
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if (success)
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fence_after(success_order);
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else
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fence_after(failure_order);
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return !!success;
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}
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static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
|
{
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storage_type original, modified;
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fence_before(order);
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__asm__ __volatile__
|
(
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"1:\n\t"
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"ldl_l %0, %2\n\t"
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"addl %0, %3, %1\n\t"
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"stl_c %1, %2\n\t"
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"beq %1, 2f\n\t"
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".subsection 2\n\t"
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"2: br 1b\n\t"
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".previous\n\t"
|
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: "=&r" (original), // %0
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"=&r" (modified) // %1
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: "m" (storage), // %2
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"r" (v) // %3
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: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
|
);
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fence_after(order);
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return original;
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}
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static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
|
{
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storage_type original, modified;
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fence_before(order);
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__asm__ __volatile__
|
(
|
"1:\n\t"
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"ldl_l %0, %2\n\t"
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"subl %0, %3, %1\n\t"
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"stl_c %1, %2\n\t"
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"beq %1, 2f\n\t"
|
|
".subsection 2\n\t"
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"2: br 1b\n\t"
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".previous\n\t"
|
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: "=&r" (original), // %0
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"=&r" (modified) // %1
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: "m" (storage), // %2
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"r" (v) // %3
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: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
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);
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fence_after(order);
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return original;
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}
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static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
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{
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storage_type original, modified;
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fence_before(order);
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__asm__ __volatile__
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(
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"1:\n\t"
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"ldl_l %0, %2\n\t"
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"and %0, %3, %1\n\t"
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"stl_c %1, %2\n\t"
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"beq %1, 2f\n\t"
|
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".subsection 2\n\t"
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"2: br 1b\n\t"
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".previous\n\t"
|
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: "=&r" (original), // %0
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"=&r" (modified) // %1
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: "m" (storage), // %2
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"r" (v) // %3
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: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
|
);
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fence_after(order);
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return original;
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}
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static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
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{
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storage_type original, modified;
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fence_before(order);
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__asm__ __volatile__
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(
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"1:\n\t"
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"ldl_l %0, %2\n\t"
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"bis %0, %3, %1\n\t"
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"stl_c %1, %2\n\t"
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"beq %1, 2f\n\t"
|
|
".subsection 2\n\t"
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"2: br 1b\n\t"
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".previous\n\t"
|
|
: "=&r" (original), // %0
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"=&r" (modified) // %1
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: "m" (storage), // %2
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"r" (v) // %3
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: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
|
);
|
fence_after(order);
|
return original;
|
}
|
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static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
|
{
|
storage_type original, modified;
|
fence_before(order);
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__asm__ __volatile__
|
(
|
"1:\n\t"
|
"ldl_l %0, %2\n\t"
|
"xor %0, %3, %1\n\t"
|
"stl_c %1, %2\n\t"
|
"beq %1, 2f\n\t"
|
|
".subsection 2\n\t"
|
"2: br 1b\n\t"
|
".previous\n\t"
|
|
: "=&r" (original), // %0
|
"=&r" (modified) // %1
|
: "m" (storage), // %2
|
"r" (v) // %3
|
: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
|
);
|
fence_after(order);
|
return original;
|
}
|
|
static BOOST_FORCEINLINE bool test_and_set(storage_type volatile& storage, memory_order order) BOOST_NOEXCEPT
|
{
|
return !!exchange(storage, (storage_type)1, order);
|
}
|
|
static BOOST_FORCEINLINE void clear(storage_type volatile& storage, memory_order order) BOOST_NOEXCEPT
|
{
|
store(storage, 0, order);
|
}
|
};
|
|
|
template< bool Interprocess >
|
struct core_arch_operations< 1u, false, Interprocess > :
|
public core_arch_operations< 4u, false, Interprocess >
|
{
|
typedef core_arch_operations< 4u, false, Interprocess > base_type;
|
typedef typename base_type::storage_type storage_type;
|
|
static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
|
{
|
storage_type original, modified;
|
base_type::fence_before(order);
|
__asm__ __volatile__
|
(
|
"1:\n\t"
|
"ldl_l %0, %2\n\t"
|
"addl %0, %3, %1\n\t"
|
"zapnot %1, 1, %1\n\t"
|
"stl_c %1, %2\n\t"
|
"beq %1, 2f\n\t"
|
|
".subsection 2\n\t"
|
"2: br 1b\n\t"
|
".previous\n\t"
|
|
: "=&r" (original), // %0
|
"=&r" (modified) // %1
|
: "m" (storage), // %2
|
"r" (v) // %3
|
: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
|
);
|
base_type::fence_after(order);
|
return original;
|
}
|
|
static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
|
{
|
storage_type original, modified;
|
base_type::fence_before(order);
|
__asm__ __volatile__
|
(
|
"1:\n\t"
|
"ldl_l %0, %2\n\t"
|
"subl %0, %3, %1\n\t"
|
"zapnot %1, 1, %1\n\t"
|
"stl_c %1, %2\n\t"
|
"beq %1, 2f\n\t"
|
|
".subsection 2\n\t"
|
"2: br 1b\n\t"
|
".previous\n\t"
|
|
: "=&r" (original), // %0
|
"=&r" (modified) // %1
|
: "m" (storage), // %2
|
"r" (v) // %3
|
: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
|
);
|
base_type::fence_after(order);
|
return original;
|
}
|
};
|
|
template< bool Interprocess >
|
struct core_arch_operations< 1u, true, Interprocess > :
|
public core_arch_operations< 4u, true, Interprocess >
|
{
|
typedef core_arch_operations< 4u, true, Interprocess > base_type;
|
typedef typename base_type::storage_type storage_type;
|
|
static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
|
{
|
storage_type original, modified;
|
base_type::fence_before(order);
|
__asm__ __volatile__
|
(
|
"1:\n\t"
|
"ldl_l %0, %2\n\t"
|
"addl %0, %3, %1\n\t"
|
"sextb %1, %1\n\t"
|
"stl_c %1, %2\n\t"
|
"beq %1, 2f\n\t"
|
|
".subsection 2\n\t"
|
"2: br 1b\n\t"
|
".previous\n\t"
|
|
: "=&r" (original), // %0
|
"=&r" (modified) // %1
|
: "m" (storage), // %2
|
"r" (v) // %3
|
: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
|
);
|
base_type::fence_after(order);
|
return original;
|
}
|
|
static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
|
{
|
storage_type original, modified;
|
base_type::fence_before(order);
|
__asm__ __volatile__
|
(
|
"1:\n\t"
|
"ldl_l %0, %2\n\t"
|
"subl %0, %3, %1\n\t"
|
"sextb %1, %1\n\t"
|
"stl_c %1, %2\n\t"
|
"beq %1, 2f\n\t"
|
|
".subsection 2\n\t"
|
"2: br 1b\n\t"
|
".previous\n\t"
|
|
: "=&r" (original), // %0
|
"=&r" (modified) // %1
|
: "m" (storage), // %2
|
"r" (v) // %3
|
: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
|
);
|
base_type::fence_after(order);
|
return original;
|
}
|
};
|
|
|
template< bool Interprocess >
|
struct core_arch_operations< 2u, false, Interprocess > :
|
public core_arch_operations< 4u, false, Interprocess >
|
{
|
typedef core_arch_operations< 4u, false, Interprocess > base_type;
|
typedef typename base_type::storage_type storage_type;
|
|
static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
|
{
|
storage_type original, modified;
|
base_type::fence_before(order);
|
__asm__ __volatile__
|
(
|
"1:\n\t"
|
"ldl_l %0, %2\n\t"
|
"addl %0, %3, %1\n\t"
|
"zapnot %1, 3, %1\n\t"
|
"stl_c %1, %2\n\t"
|
"beq %1, 2f\n\t"
|
|
".subsection 2\n\t"
|
"2: br 1b\n\t"
|
".previous\n\t"
|
|
: "=&r" (original), // %0
|
"=&r" (modified) // %1
|
: "m" (storage), // %2
|
"r" (v) // %3
|
: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
|
);
|
base_type::fence_after(order);
|
return original;
|
}
|
|
static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
|
{
|
storage_type original, modified;
|
base_type::fence_before(order);
|
__asm__ __volatile__
|
(
|
"1:\n\t"
|
"ldl_l %0, %2\n\t"
|
"subl %0, %3, %1\n\t"
|
"zapnot %1, 3, %1\n\t"
|
"stl_c %1, %2\n\t"
|
"beq %1, 2f\n\t"
|
|
".subsection 2\n\t"
|
"2: br 1b\n\t"
|
".previous\n\t"
|
|
: "=&r" (original), // %0
|
"=&r" (modified) // %1
|
: "m" (storage), // %2
|
"r" (v) // %3
|
: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
|
);
|
base_type::fence_after(order);
|
return original;
|
}
|
};
|
|
template< bool Interprocess >
|
struct core_arch_operations< 2u, true, Interprocess > :
|
public core_arch_operations< 4u, true, Interprocess >
|
{
|
typedef core_arch_operations< 4u, true, Interprocess > base_type;
|
typedef typename base_type::storage_type storage_type;
|
|
static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
|
{
|
storage_type original, modified;
|
base_type::fence_before(order);
|
__asm__ __volatile__
|
(
|
"1:\n\t"
|
"ldl_l %0, %2\n\t"
|
"addl %0, %3, %1\n\t"
|
"sextw %1, %1\n\t"
|
"stl_c %1, %2\n\t"
|
"beq %1, 2f\n\t"
|
|
".subsection 2\n\t"
|
"2: br 1b\n\t"
|
".previous\n\t"
|
|
: "=&r" (original), // %0
|
"=&r" (modified) // %1
|
: "m" (storage), // %2
|
"r" (v) // %3
|
: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
|
);
|
base_type::fence_after(order);
|
return original;
|
}
|
|
static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
|
{
|
storage_type original, modified;
|
base_type::fence_before(order);
|
__asm__ __volatile__
|
(
|
"1:\n\t"
|
"ldl_l %0, %2\n\t"
|
"subl %0, %3, %1\n\t"
|
"sextw %1, %1\n\t"
|
"stl_c %1, %2\n\t"
|
"beq %1, 2f\n\t"
|
|
".subsection 2\n\t"
|
"2: br 1b\n\t"
|
".previous\n\t"
|
|
: "=&r" (original), // %0
|
"=&r" (modified) // %1
|
: "m" (storage), // %2
|
"r" (v) // %3
|
: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
|
);
|
base_type::fence_after(order);
|
return original;
|
}
|
};
|
|
|
template< bool Signed, bool Interprocess >
|
struct core_arch_operations< 8u, Signed, Interprocess > :
|
public core_arch_operations_gcc_alpha_base
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{
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typedef typename storage_traits< 8u >::type storage_type;
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static BOOST_CONSTEXPR_OR_CONST std::size_t storage_size = 8u;
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static BOOST_CONSTEXPR_OR_CONST std::size_t storage_alignment = 8u;
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static BOOST_CONSTEXPR_OR_CONST bool is_signed = Signed;
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static BOOST_CONSTEXPR_OR_CONST bool is_interprocess = Interprocess;
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static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
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{
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fence_before(order);
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storage = v;
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fence_after_store(order);
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}
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static BOOST_FORCEINLINE storage_type load(storage_type const volatile& storage, memory_order order) BOOST_NOEXCEPT
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{
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storage_type v = storage;
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fence_after(order);
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return v;
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}
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static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
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{
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storage_type original, tmp;
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fence_before(order);
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__asm__ __volatile__
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(
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"1:\n\t"
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"mov %3, %1\n\t"
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"ldq_l %0, %2\n\t"
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"stq_c %1, %2\n\t"
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"beq %1, 2f\n\t"
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".subsection 2\n\t"
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"2: br 1b\n\t"
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".previous\n\t"
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: "=&r" (original), // %0
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"=&r" (tmp) // %1
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: "m" (storage), // %2
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"r" (v) // %3
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: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
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);
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fence_after(order);
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return original;
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}
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static BOOST_FORCEINLINE bool compare_exchange_weak(
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storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
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{
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fence_before(success_order);
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int success;
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storage_type current;
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__asm__ __volatile__
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(
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"1:\n\t"
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"ldq_l %2, %4\n\t" // current = *(&storage)
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"cmpeq %2, %0, %3\n\t" // success = current == expected
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"mov %2, %0\n\t" // expected = current
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"beq %3, 2f\n\t" // if (success == 0) goto end
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"stq_c %1, %4\n\t" // storage = desired; desired = store succeeded
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"mov %1, %3\n\t" // success = desired
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"2:\n\t"
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: "+r" (expected), // %0
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"+r" (desired), // %1
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"=&r" (current), // %2
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"=&r" (success) // %3
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: "m" (storage) // %4
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: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
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);
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if (success)
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fence_after(success_order);
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else
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fence_after(failure_order);
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return !!success;
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}
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static BOOST_FORCEINLINE bool compare_exchange_strong(
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storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
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{
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int success;
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storage_type current, tmp;
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fence_before(success_order);
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__asm__ __volatile__
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(
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"1:\n\t"
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"mov %5, %1\n\t" // tmp = desired
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"ldq_l %2, %4\n\t" // current = *(&storage)
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"cmpeq %2, %0, %3\n\t" // success = current == expected
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"mov %2, %0\n\t" // expected = current
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"beq %3, 2f\n\t" // if (success == 0) goto end
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"stq_c %1, %4\n\t" // storage = tmp; tmp = store succeeded
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"beq %1, 3f\n\t" // if (tmp == 0) goto retry
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"mov %1, %3\n\t" // success = tmp
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"2:\n\t"
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".subsection 2\n\t"
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"3: br 1b\n\t"
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".previous\n\t"
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: "+r" (expected), // %0
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"=&r" (tmp), // %1
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"=&r" (current), // %2
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"=&r" (success) // %3
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: "m" (storage), // %4
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"r" (desired) // %5
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: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
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);
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if (success)
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fence_after(success_order);
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else
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fence_after(failure_order);
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return !!success;
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}
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static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
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{
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storage_type original, modified;
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fence_before(order);
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__asm__ __volatile__
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(
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"1:\n\t"
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"ldq_l %0, %2\n\t"
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"addq %0, %3, %1\n\t"
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"stq_c %1, %2\n\t"
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"beq %1, 2f\n\t"
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".subsection 2\n\t"
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"2: br 1b\n\t"
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".previous\n\t"
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: "=&r" (original), // %0
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"=&r" (modified) // %1
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: "m" (storage), // %2
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"r" (v) // %3
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: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
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);
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fence_after(order);
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return original;
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}
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static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
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{
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storage_type original, modified;
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fence_before(order);
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__asm__ __volatile__
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(
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"1:\n\t"
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"ldq_l %0, %2\n\t"
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"subq %0, %3, %1\n\t"
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"stq_c %1, %2\n\t"
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"beq %1, 2f\n\t"
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".subsection 2\n\t"
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"2: br 1b\n\t"
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".previous\n\t"
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: "=&r" (original), // %0
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"=&r" (modified) // %1
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: "m" (storage), // %2
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"r" (v) // %3
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: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
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);
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fence_after(order);
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return original;
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}
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static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
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{
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storage_type original, modified;
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fence_before(order);
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__asm__ __volatile__
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(
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"1:\n\t"
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"ldq_l %0, %2\n\t"
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"and %0, %3, %1\n\t"
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"stq_c %1, %2\n\t"
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"beq %1, 2f\n\t"
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".subsection 2\n\t"
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"2: br 1b\n\t"
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".previous\n\t"
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: "=&r" (original), // %0
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"=&r" (modified) // %1
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: "m" (storage), // %2
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"r" (v) // %3
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: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
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);
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fence_after(order);
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return original;
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}
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static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
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{
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storage_type original, modified;
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fence_before(order);
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__asm__ __volatile__
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(
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"1:\n\t"
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"ldq_l %0, %2\n\t"
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"bis %0, %3, %1\n\t"
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"stq_c %1, %2\n\t"
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"beq %1, 2f\n\t"
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".subsection 2\n\t"
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"2: br 1b\n\t"
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".previous\n\t"
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: "=&r" (original), // %0
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"=&r" (modified) // %1
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: "m" (storage), // %2
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"r" (v) // %3
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: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
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);
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fence_after(order);
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return original;
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}
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static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
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{
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storage_type original, modified;
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fence_before(order);
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__asm__ __volatile__
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(
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"1:\n\t"
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"ldq_l %0, %2\n\t"
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"xor %0, %3, %1\n\t"
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"stq_c %1, %2\n\t"
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"beq %1, 2f\n\t"
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".subsection 2\n\t"
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"2: br 1b\n\t"
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".previous\n\t"
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: "=&r" (original), // %0
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"=&r" (modified) // %1
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: "m" (storage), // %2
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"r" (v) // %3
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: BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
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);
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fence_after(order);
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return original;
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}
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static BOOST_FORCEINLINE bool test_and_set(storage_type volatile& storage, memory_order order) BOOST_NOEXCEPT
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{
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return !!exchange(storage, (storage_type)1, order);
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}
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static BOOST_FORCEINLINE void clear(storage_type volatile& storage, memory_order order) BOOST_NOEXCEPT
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{
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store(storage, (storage_type)0, order);
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}
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};
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} // namespace detail
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} // namespace atomics
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} // namespace boost
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#include <boost/atomic/detail/footer.hpp>
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#endif // BOOST_ATOMIC_DETAIL_CORE_ARCH_OPS_GCC_ALPHA_HPP_INCLUDED_
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