/*
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* Distributed under the Boost Software License, Version 1.0.
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* (See accompanying file LICENSE_1_0.txt or copy at
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* http://www.boost.org/LICENSE_1_0.txt)
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*
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* Copyright (c) 2009 Helge Bahmann
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* Copyright (c) 2013 Tim Blechmann
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* Copyright (c) 2014, 2020 Andrey Semashev
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*/
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/*!
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* \file atomic/detail/gcc_arm_asm_common.hpp
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*
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* This header contains basic utilities for gcc asm-based ARM backend.
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*/
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#ifndef BOOST_ATOMIC_DETAIL_GCC_ARM_ASM_COMMON_HPP_INCLUDED_
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#define BOOST_ATOMIC_DETAIL_GCC_ARM_ASM_COMMON_HPP_INCLUDED_
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#include <boost/atomic/detail/config.hpp>
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#include <boost/atomic/detail/capabilities.hpp>
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// A memory barrier is effected using a "co-processor 15" instruction,
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// though a separate assembler mnemonic is available for it in v7.
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//
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// "Thumb 1" is a subset of the ARM instruction set that uses a 16-bit encoding. It
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// doesn't include all instructions and in particular it doesn't include the co-processor
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// instruction used for the memory barrier or the load-locked/store-conditional
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// instructions. So, if we're compiling in "Thumb 1" mode, we need to wrap all of our
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// asm blocks with code to temporarily change to ARM mode.
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//
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// You can only change between ARM and Thumb modes when branching using the bx instruction.
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// bx takes an address specified in a register. The least significant bit of the address
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// indicates the mode, so 1 is added to indicate that the destination code is Thumb.
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// A temporary register is needed for the address and is passed as an argument to these
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// macros. It must be one of the "low" registers accessible to Thumb code, specified
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// using the "l" attribute in the asm statement.
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//
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// Architecture v7 introduces "Thumb 2", which does include (almost?) all of the ARM
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// instruction set. (Actually, there was an extension of v6 called v6T2 which supported
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// "Thumb 2" mode, but its architecture manual is no longer available, referring to v7.)
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// So in v7 we don't need to change to ARM mode; we can write "universal
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// assembler" which will assemble to Thumb 2 or ARM code as appropriate. The only thing
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// we need to do to make this "universal" assembler mode work is to insert "IT" instructions
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// to annotate the conditional instructions. These are ignored in other modes (e.g. v6),
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// so they can always be present.
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// A note about memory_order_consume. Technically, this architecture allows to avoid
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// unnecessary memory barrier after consume load since it supports data dependency ordering.
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// However, some compiler optimizations may break a seemingly valid code relying on data
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// dependency tracking by injecting bogus branches to aid out of order execution.
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// This may happen not only in Boost.Atomic code but also in user's code, which we have no
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// control of. See this thread: http://lists.boost.org/Archives/boost/2014/06/213890.php.
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// For this reason we promote memory_order_consume to memory_order_acquire.
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#if defined(__thumb__) && !defined(__thumb2__)
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#define BOOST_ATOMIC_DETAIL_ARM_ASM_START(TMPREG) "adr " #TMPREG ", 8f\n\t" "bx " #TMPREG "\n\t" ".arm\n\t" ".align 4\n\t" "8:\n\t"
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#define BOOST_ATOMIC_DETAIL_ARM_ASM_END(TMPREG) "adr " #TMPREG ", 9f + 1\n\t" "bx " #TMPREG "\n\t" ".thumb\n\t" ".align 2\n\t" "9:\n\t"
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#define BOOST_ATOMIC_DETAIL_ARM_ASM_TMPREG_CONSTRAINT(var) "=&l" (var)
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#else
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// Indicate that start/end macros are empty and the tmpreg is not needed
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#define BOOST_ATOMIC_DETAIL_ARM_ASM_TMPREG_UNUSED
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#define BOOST_ATOMIC_DETAIL_ARM_ASM_START(TMPREG)
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#define BOOST_ATOMIC_DETAIL_ARM_ASM_END(TMPREG)
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#define BOOST_ATOMIC_DETAIL_ARM_ASM_TMPREG_CONSTRAINT(var) "=&l" (var)
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#endif
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#if defined(BOOST_ATOMIC_DETAIL_ARM_LITTLE_ENDIAN)
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#define BOOST_ATOMIC_DETAIL_ARM_ASM_ARG_LO(arg) "%" BOOST_STRINGIZE(arg)
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#define BOOST_ATOMIC_DETAIL_ARM_ASM_ARG_HI(arg) "%H" BOOST_STRINGIZE(arg)
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#else
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#define BOOST_ATOMIC_DETAIL_ARM_ASM_ARG_LO(arg) "%H" BOOST_STRINGIZE(arg)
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#define BOOST_ATOMIC_DETAIL_ARM_ASM_ARG_HI(arg) "%" BOOST_STRINGIZE(arg)
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#endif
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#endif // BOOST_ATOMIC_DETAIL_GCC_ARM_ASM_COMMON_HPP_INCLUDED_
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