#ifndef THC_REDUCE_INC
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#define THC_REDUCE_INC
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//
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// This file contains dimension reduction operation functions and
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// kernels that work on both contiguous and non-contiguous tensor
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// arguments of arbitrary (up to MAX_CUTORCH_DIMS) dimensioned
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// arguments without copying or temporary storage.
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//
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#include <THC/THCTensorTypeUtils.cuh>
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#include <THC/THCReduceApplyUtils.cuh>
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#include <THC/THCNumerics.cuh>
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#include <c10/macros/Macros.h>
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// Threads per thread block
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#define THC_NONCONTIG_REDUCE_BLOCK_SIZE 32 * 16
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#define CHUNKPERBLOCK 256
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template <typename IndexType>
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__device__ __forceinline__ IndexType getReduceNoncontigDimSliceIndex() {
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// Each thread handles one slice
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return getLinearBlockId<IndexType>() * THC_NONCONTIG_REDUCE_BLOCK_SIZE + threadIdx.x;
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}
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// quick hack to enable two-stage use of reduceChunk
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template <typename T>
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struct SimpleCopyOp
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{
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__device__ __forceinline__ T operator()(volatile const T val) const volatile
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{
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return val;
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}
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};
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__device__ __forceinline__ int lastpow2(int n)
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{
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int out = 1 << (31 - __clz(n));
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if(n == out)
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out >>= 1;
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return out;
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}
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template
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<typename T,
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typename U,
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typename IndexType,
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typename AccT,
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typename ModifyOp,
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typename ReduceOp,
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typename FinalizeOp>
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__device__ __forceinline__ void reduceChunk
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(T* out,
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U* in,
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const int& inbounds,
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const IndexType& reductionStride,
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const IndexType& reductionSize,
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const IndexType& inOffset,
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const IndexType& outOffset,
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const int& shmem_lim,
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AccT init,
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AccT* shmem,
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ModifyOp modifyOp,
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ReduceOp reduceOp,
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FinalizeOp finalizeOp)
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{
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AccT load_reg[4];
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AccT local_reg = init;
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//Unroll this loop
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//for(IndexType i=threadIdx.y; i<reductionSize; i+=blockDim.y){
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// local_reg += in[inOffset + i*reductionStride];
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//}
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if(inbounds)
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for(IndexType i = threadIdx.y; i < reductionSize; i += blockDim.y*4)
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{
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if (i + blockDim.y*3 < reductionSize)
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{
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const AccT val0 = scalar_cast<AccT>(in[inOffset + i*reductionStride]);
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load_reg[0] = modifyOp(val0);
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const AccT val1 = scalar_cast<AccT>(in[inOffset + (i + blockDim.y)*reductionStride]);
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load_reg[1] = modifyOp(val1);
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const AccT val2 = scalar_cast<AccT>(in[inOffset + (i + blockDim.y*2)*reductionStride]);
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load_reg[2] = modifyOp(val2);
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const AccT val3 = scalar_cast<AccT>(in[inOffset + (i + blockDim.y*3)*reductionStride]);
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load_reg[3] = modifyOp(val3);
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local_reg = reduceOp(local_reg, load_reg[0]);
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local_reg = reduceOp(local_reg, load_reg[1]);
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local_reg = reduceOp(local_reg, load_reg[2]);
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local_reg = reduceOp(local_reg, load_reg[3]);
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}
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else if (i + blockDim.y*2 < reductionSize)
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{
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const AccT val0 = scalar_cast<AccT>(in[inOffset + i*reductionStride]);
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load_reg[0] = modifyOp(val0);
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const AccT val1 = scalar_cast<AccT>(in[inOffset + (i + blockDim.y)*reductionStride]);
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load_reg[1] = modifyOp(val1);
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const AccT val2 = scalar_cast<AccT>(in[inOffset + (i + blockDim.y*2)*reductionStride]);
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load_reg[2] = modifyOp(val2);
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local_reg = reduceOp(local_reg, load_reg[0]);
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local_reg = reduceOp(local_reg, load_reg[1]);
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local_reg = reduceOp(local_reg, load_reg[2]);
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}
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else if (i + blockDim.y < reductionSize)
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{
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const AccT val0 = scalar_cast<AccT>(in[inOffset + i*reductionStride]);
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load_reg[0] = modifyOp(val0);
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const AccT val1 = scalar_cast<AccT>(in[inOffset + (i + blockDim.y)*reductionStride]);
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load_reg[1] = modifyOp(val1);
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local_reg = reduceOp(local_reg, load_reg[0]);
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local_reg = reduceOp(local_reg, load_reg[1]);
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}
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else if (i < reductionSize)
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{
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const AccT val0 = scalar_cast<AccT>(in[inOffset + i*reductionStride]);
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local_reg = reduceOp(local_reg, modifyOp(val0));
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}
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}
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*shmem = local_reg;
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for(int i = lastpow2(shmem_lim); i > 0; i >>= 1)
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{
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__syncthreads();
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if(threadIdx.y < i && threadIdx.y + i < shmem_lim)
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*shmem = reduceOp(*shmem, *(shmem + i*blockDim.x));
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}
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if(threadIdx.y == 0 && inbounds) {
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T &&o_ele = static_cast<T>(finalizeOp(*shmem));
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out[outOffset] = o_ele;
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}
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}
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// Kernel that handles an entire reduction of a slice of a tensor per each thread
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template
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<typename T,
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typename IndexType,
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typename AccT,
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typename ModifyOp,
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typename ReduceOp,
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typename FinalizeOp,
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int ADims, int BDims>
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#if __CUDA_ARCH__ >= 350 || defined __HIP_PLATFORM_HCC__
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C10_LAUNCH_BOUNDS_2(512, 4)
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#endif
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__global__ void kernelReduceNoncontigDim_shared
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(TensorInfo<T, IndexType> out,
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TensorInfo<T, IndexType> in,
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IndexType reductionStride,
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IndexType reductionSize,
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IndexType totalSlices,
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AccT init,
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ModifyOp modifyOp,
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ReduceOp reduceOp,
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FinalizeOp finalizeOp,
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volatile AccT* stagingData,
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int* semaphores)
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{
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IndexType sliceIndex = blockIdx.x*blockDim.x + threadIdx.x;
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__shared__ int isLastBlockDone;
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__shared__ AccT local_reduce[THC_NONCONTIG_REDUCE_BLOCK_SIZE];
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AccT* shmem = &local_reduce[threadIdx.x + threadIdx.y*blockDim.x];
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// This kernel is intended for the latency-bound case, so we want to launch enough blocks
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// to cover the entire output. This means we don't need grid-stride loops.
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const IndexType outOffset =
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IndexToOffset<T, IndexType, ADims>::get(sliceIndex, out);
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const IndexType inOffset =
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IndexToOffset<T, IndexType, BDims>::get(sliceIndex, in);
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const int inbounds = (sliceIndex < totalSlices);
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if(gridDim.y == 1)
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reduceChunk
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(out.data,
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in.data,
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inbounds,
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reductionStride,
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reductionSize,
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inOffset,
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outOffset,
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reductionSize < blockDim.y ? reductionSize : blockDim.y,
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init,
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shmem,
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modifyOp,
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reduceOp,
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finalizeOp);
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else
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{
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int* semaphore = semaphores + blockIdx.x;
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const IndexType chunkStart = blockIdx.y*CHUNKPERBLOCK;
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const IndexType chunkSize = reductionSize - chunkStart < CHUNKPERBLOCK ?
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reductionSize - chunkStart : CHUNKPERBLOCK;
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const IndexType reductionStrideStaging = totalSlices;
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const IndexType stagingOffset = sliceIndex;
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reduceChunk
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(stagingData,
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in.data,
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inbounds,
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reductionStride,
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chunkSize,
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inOffset + chunkStart*reductionStride,
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stagingOffset + blockIdx.y*reductionStrideStaging,
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chunkSize < blockDim.y ? chunkSize : blockDim.y,
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init,
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shmem,
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modifyOp,
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reduceOp,
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SimpleCopyOp<AccT>());
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__threadfence(); // make sure writes are globally visible
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__syncthreads(); // if multiple warps in this block wrote to staging, make sure they're all done
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if(threadIdx.x == 0 && threadIdx.y == 0)
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{
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int old = atomicAdd(semaphore, 1);
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isLastBlockDone = (old == gridDim.y - 1);
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}
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__syncthreads();
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// The staging area contains gridDim.y elements along each slice. The final reduction
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// begins by treating the first blockDim.y elements as "init" values.
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if(isLastBlockDone)
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{
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if(threadIdx.y < gridDim.y)
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init = stagingData[stagingOffset + threadIdx.y*reductionStrideStaging];
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IndexType remaining = gridDim.y < blockDim.y ? 0 : gridDim.y - blockDim.y;
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reduceChunk
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(out.data,
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stagingData,
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inbounds,
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reductionStrideStaging,
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remaining, // if 0, loop in reduceChunk is skipped, otherwise...
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stagingOffset + blockDim.y*reductionStrideStaging, // ...loop begins at blockDim+1th element
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outOffset,
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gridDim.y < blockDim.y ? gridDim.y : blockDim.y,
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init,
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shmem,
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SimpleCopyOp<AccT>(),
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reduceOp,
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finalizeOp);
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}
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}
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}
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// Kernel that handles an entire reduction of a slice of a tensor per each thread
|
template <typename T,
|
typename IndexType,
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typename AccT,
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typename ModifyOp,
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typename ReduceOp,
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typename FinalizeOp,
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int ADims, int BDims>
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#if __CUDA_ARCH__ >= 350 || defined __HIP_PLATFORM_HCC__
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C10_LAUNCH_BOUNDS_2(512, 4)
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#endif
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__global__ void
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kernelReduceNoncontigDim(TensorInfo<T, IndexType> out,
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TensorInfo<T, IndexType> in,
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IndexType reductionStride,
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IndexType reductionSize,
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IndexType totalSlices,
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AccT init,
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ModifyOp modifyOp,
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ReduceOp reduceOp,
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FinalizeOp finalizeOp) {
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const IndexType sliceIndex = getReduceNoncontigDimSliceIndex<IndexType>();
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if (sliceIndex >= totalSlices) {
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return;
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}
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// Each thread picks a point in `out` and `in` for which it is
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// producing the reduction
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const IndexType outOffset =
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IndexToOffset<T, IndexType, ADims>::get(sliceIndex, out);
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const IndexType inBaseOffset =
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IndexToOffset<T, IndexType, BDims>::get(sliceIndex, in);
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// For each point in reductionSize, reduce into `r`
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IndexType inOffset = inBaseOffset;
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AccT r = init;
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for (IndexType i = 0; i < reductionSize; ++i) {
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const AccT val = scalar_cast<AccT>(in.data[inOffset]);
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r = reduceOp(r, modifyOp(val));
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inOffset += reductionStride;
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}
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// Write out reduced value
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out.data[outOffset] = scalar_cast<T>(finalizeOp(r));
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}
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template <typename IndexType>
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__device__ __forceinline__ IndexType getReduceContigDimSliceIndex() {
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// Each block handles one slice
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return getLinearBlockId<IndexType>();
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}
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// Kernel that handles an entire reduction of a slice of a tensor per
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// each block
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template <typename T,
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typename IndexType,
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typename AccT,
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typename ModifyOp,
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typename ReduceOp,
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typename FinalizeOp,
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int ADims, int BDims>
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__global__ void
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kernelReduceContigDim(TensorInfo<T, IndexType> out,
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TensorInfo<T, IndexType> in,
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IndexType reductionSize,
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IndexType totalSlices,
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AccT init,
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ModifyOp modifyOp,
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ReduceOp reduceOp,
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FinalizeOp finalizeOp) {
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const IndexType sliceIndex = getReduceContigDimSliceIndex<IndexType>();
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if (sliceIndex >= totalSlices) {
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return;
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}
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// Get the offset in `out` for the reduction
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const IndexType outOffset =
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IndexToOffset<T, IndexType, ADims>::get(sliceIndex, out);
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// Get the base offset in `in` for this block's reduction
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const IndexType inBaseOffset =
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IndexToOffset<T, IndexType, BDims>::get(sliceIndex, in);
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// Each thread in the block will reduce some subset of elements in
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// the slice. The elements are guaranteed contiguous starting at
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// `inBaseOffset`.
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AccT r = init;
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for (IndexType i = threadIdx.x; i < reductionSize; i += blockDim.x) {
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const AccT val = scalar_cast<AccT>(in.data[inBaseOffset + i]);
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r = reduceOp(r, modifyOp(val));
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}
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// Reduce within the block
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// FIXME: extern name
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extern __shared__ char smemChar[];
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AccT* smem = (AccT*) smemChar;
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r = reduceBlock<AccT, ReduceOp>(smem, blockDim.x, r, reduceOp, init);
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if (threadIdx.x == 0) {
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// Write out reduced value
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out.data[outOffset] = scalar_cast<T>(finalizeOp(r));
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}
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}
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inline dim3 getNoncontigReduceBlock() {
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return dim3(THC_NONCONTIG_REDUCE_BLOCK_SIZE);
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}
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inline dim3 getContigReduceBlock(ptrdiff_t numSlices, int64_t reductionSize) {
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// If the number of slices is low but the reduction dimension size
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// is high, then we should increase block size for greater parallelism.
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// Aim for at least 32 warps per SM (assume 15 SMs; don't bother
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// inquiring the real number for now).
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int maxWarps = 4; // better occupancy if many blocks are around
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// For numSlices > 15 * 8, there are > 32 warps active per SM.
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if (numSlices < 15 * 8) {
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maxWarps = 8;
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if (numSlices < 15 * 4) {
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maxWarps = 16;
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if (numSlices < 15 * 2) {
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maxWarps = 32;
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}
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}
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}
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// Scale up block size based on the reduction dimension size
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int64_t warpsInReductionSize = THCCeilDiv(reductionSize, (int64_t) 32);
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int numWarps = warpsInReductionSize > (int64_t) maxWarps ?
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maxWarps : (int) warpsInReductionSize;
|
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return dim3(numWarps * 32);
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}
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inline bool getNoncontigReduceGrid(ptrdiff_t elements, dim3& grid) {
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// One output point per thread
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return THC_getGridFromTiles(THCCeilDiv(elements,
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(ptrdiff_t) THC_NONCONTIG_REDUCE_BLOCK_SIZE), grid);
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}
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inline bool getContigReduceGrid(ptrdiff_t elements, dim3& grid) {
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// One output point per block
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return THC_getGridFromTiles(elements, grid);
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}
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// Performs a reduction out[..., 0, ...] = reduce_i(modify(in[..., i, ...])) for
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// all in where i and the out's 0 are indexed at dimension `dim`
|
template <typename ScalarType,
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typename TensorType,
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typename ModifyOp,
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typename ReduceOp,
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typename FinalizeOp,
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typename AccT>
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bool THC_reduceDim(THCState* state,
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TensorType* out,
|
TensorType* in,
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const ModifyOp modifyOp,
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const ReduceOp reduceOp,
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const FinalizeOp finalizeOp,
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AccT init,
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int dim,
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int keepdim) {
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ptrdiff_t inElements = THCTensor_nElement(state, in);
|
|
int64_t reductionSize = THTensor_sizeLegacyNoScalars(in, dim);
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int64_t reductionStride = THTensor_strideLegacyNoScalars(in, dim);
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ptrdiff_t outElements = inElements / reductionSize;
|
|
if (THCTensor_nDimensionLegacyAll(state, out) > MAX_CUTORCH_DIMS ||
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THCTensor_nDimensionLegacyAll(state, in) > MAX_CUTORCH_DIMS) {
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return false;
|
}
|
|
if (THCTensor_nDimensionLegacyAll(state, in) == 0) {
|
// Zero-dim tensor; do nothing
|
return true;
|
}
|
|
// Is the reduction dimension contiguous? If so, then we can use a
|
// shared memory reduction kernel to increase performance.
|
bool contigReduction = (reductionStride == 1);
|
|
dim3 block;
|
dim3 grid;
|
int smemSize = 0; // contiguous reduction uses smem
|
if (contigReduction) {
|
if (!getContigReduceGrid(outElements, grid)) {
|
return false;
|
}
|
|
block = getContigReduceBlock(outElements, reductionSize);
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smemSize = sizeof(AccT) * block.x;
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} else {
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if (!getNoncontigReduceGrid(outElements, grid)) {
|
return false;
|
}
|
|
block = getNoncontigReduceBlock();
|
|
if(outElements <= 4096)
|
{
|
// gridDim.x and blockDim.x parallelize work across slices.
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// blockDim.y enables some intra-block reduction within slices.
|
// gridDim.y enables inter-block reduction within slices.
|
|
// Each block covers 32 output elements.
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int blockdimx = 32;
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int griddimx = THCCeilDiv((int64_t)outElements, (int64_t)blockdimx);
|
|
// Each warp reduces at most 4 slices. This heuristic can be tuned,
|
// but locking blockdimy to 16 is robust and reasonably performant.
|
int blockdimy = 16;
|
|
int griddimy = 1;
|
bool coop = false;
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// Rough heuristics to decide if using cooperating blocks is worthwhile
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if( outElements <= 32 && reductionSize >= 4096) coop = true;
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if( 32 < outElements && outElements <= 64 && reductionSize >= 4096) coop = true;
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if( 64 < outElements && outElements <= 128 && reductionSize >= 4096) coop = true;
|
if( 128 < outElements && outElements <= 256 && reductionSize >= 4096) coop = true;
|
if( 256 < outElements && outElements <= 512 && reductionSize >= 4096) coop = true;
|
if( 512 < outElements && outElements <= 1024 && reductionSize >= 4096) coop = true;
|
if(1024 < outElements && outElements <= 2048 && reductionSize >= 2048) coop = true;
|
if(2048 < outElements && outElements <= 4096 && reductionSize >= 2048) coop = true;
|
// Each block reduces at most CHUNKPERBLOCK (currently 256) slices.
|
if(coop)
|
griddimy = THCCeilDiv((int64_t)reductionSize, (int64_t)CHUNKPERBLOCK);
|
|
grid = dim3(griddimx, griddimy, 1);
|
block = dim3(blockdimx, blockdimy, 1);
|
}
|
}
|
|
// Resize out to correspond to the reduced size with keepdim=True.
|
|
// Preserve noncontiguities by unsqueezing out if necessary
|
THCTensor_preserveReduceDimSemantics(
|
state, out, THCTensor_nDimensionLegacyAll(state, in), dim, keepdim);
|
|
// Resize out
|
std::vector<int64_t> sizes = THTensor_sizesLegacyNoScalars(in);
|
sizes[dim] = 1;
|
THCTensor_resize(state, out, sizes, {});
|
|
// It is possible that the tensor dimensions are able to be collapsed,
|
// and thus we can reduce the actual code complexity of the copy by
|
// exploiting this knowledge statically, since the div/mod is the
|
// most expensive part of the operation, more so than memory accesses.
|
// For instance, when copying a non-contiguous to a contiguous tensor
|
// (or vice versa), the contiguous tensor can be collapsed to one
|
// dimension, and the loop to translate the linear index to the array
|
// index can be similarly collapsed. That is what this unrolling is for.
|
#define HANDLE_CASE(TYPE, OUT, IN) \
|
if (contigReduction) { \
|
kernelReduceContigDim<ScalarType, \
|
TYPE, AccT, ModifyOp, ReduceOp, FinalizeOp, \
|
OUT, IN> \
|
<<<grid, block, smemSize, THCState_getCurrentStream(state)>>> \
|
(outInfo, inInfo, reductionSize, \
|
(TYPE) outElements, init, modifyOp, reduceOp, finalizeOp); \
|
} else { \
|
if(block.y == 1){ \
|
kernelReduceNoncontigDim< \
|
ScalarType, \
|
TYPE, AccT, ModifyOp, ReduceOp, FinalizeOp, \
|
OUT, IN> \
|
<<<grid, block, 0, THCState_getCurrentStream(state)>>> \
|
(outInfo, inInfo, reductionStride, reductionSize, \
|
(TYPE) outElements, init, modifyOp, reduceOp, finalizeOp); \
|
} \
|
else \
|
{ \
|
void* stagingData = nullptr; \
|
void* semaphores = nullptr; \
|
\
|
if(grid.y > 1) \
|
{ \
|
stagingData = THCudaMalloc(state, sizeof(AccT)*outElements*grid.y);\
|
semaphores = THCudaMalloc(state, sizeof(int)*grid.x); \
|
THCudaCheck(cudaMemsetAsync \
|
(semaphores, \
|
0, \
|
sizeof(int)*grid.x, \
|
THCState_getCurrentStream(state))); \
|
} \
|
\
|
kernelReduceNoncontigDim_shared \
|
<ScalarType, TYPE, AccT, ModifyOp, ReduceOp, FinalizeOp, OUT, IN> \
|
<<<grid, block, 0, THCState_getCurrentStream(state)>>> \
|
(outInfo, \
|
inInfo, \
|
reductionStride, \
|
reductionSize, \
|
(TYPE) outElements, \
|
init, \
|
modifyOp, \
|
reduceOp, \
|
finalizeOp, \
|
(volatile AccT*)stagingData, \
|
(int*)semaphores); \
|
\
|
if(grid.y > 1) \
|
{ \
|
THCudaFree(state, stagingData); \
|
THCudaFree(state, semaphores); \
|
} \
|
} \
|
}
|
|
#define HANDLE_IN_CASE(TYPE, OUT, IN) \
|
{ \
|
switch (IN) { \
|
case 1: \
|
HANDLE_CASE(TYPE, OUT, 1); \
|
break; \
|
case 2: \
|
HANDLE_CASE(TYPE, OUT, 2); \
|
break; \
|
default: \
|
HANDLE_CASE(TYPE, OUT, -1); \
|
break; \
|
} \
|
}
|
|
#define HANDLE_OUT_CASE(TYPE, OUT, IN) \
|
{ \
|
switch (OUT) { \
|
case 1: \
|
HANDLE_IN_CASE(TYPE, 1, IN); \
|
break; \
|
case 2: \
|
HANDLE_IN_CASE(TYPE, 2, IN); \
|
break; \
|
default: \
|
HANDLE_IN_CASE(TYPE, -1, IN); \
|
break; \
|
} \
|
}
|
|
if(THCTensor_canUse32BitIndexMath(state, out) &&
|
THCTensor_canUse32BitIndexMath(state, in))
|
{
|
TensorInfo<ScalarType,
|
unsigned int> outInfo =
|
getTensorInfo<ScalarType, TensorType, unsigned int>(state, out);
|
outInfo.collapseDims();
|
|
TensorInfo<ScalarType,
|
unsigned int> inInfo =
|
getTensorInfo<ScalarType, TensorType, unsigned int>(state, in);
|
inInfo.reduceDim(dim);
|
inInfo.collapseDims();
|
HANDLE_OUT_CASE(unsigned int, outInfo.dims, inInfo.dims);
|
}
|
else
|
{
|
TensorInfo<ScalarType,
|
uint64_t> outInfo =
|
getTensorInfo<ScalarType, TensorType, uint64_t>(state, out);
|
outInfo.collapseDims();
|
|
TensorInfo<ScalarType,
|
uint64_t> inInfo =
|
getTensorInfo<ScalarType, TensorType, uint64_t>(state, in);
|
inInfo.reduceDim(dim);
|
inInfo.collapseDims();
|
|
/*
|
Only instantiates the all 1D special case and the fallback all nD case for
|
large (64-bit indexed) tensors to reduce compilation time.
|
*/
|
if (outInfo.dims == 1 && inInfo.dims == 1) {
|
HANDLE_CASE(uint64_t, 1, 1);
|
} else {
|
HANDLE_CASE(uint64_t, -1, -1);
|
}
|
}
|
#undef HANDLE_CASE
|
#undef HANDLE_IN_CASE
|
#undef HANDLE_OUT_CASE
|
|
|
if (!keepdim) {
|
THCTensor_squeeze1d(state, out, out, dim);
|
}
|
return true;
|
}
|
|
#undef THC_NONCONTIG_REDUCE_BLOCK_SIZE
|
#undef CHUNKPERBLOCK
|
|
#endif // THC_REDUCE_INC
|
